1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a thin film transistor array substrate and a method of manufacturing the same.
2. Description of the Related Art
In general, a liquid crystal display device outputs an image by adjusting a transmittance of a liquid crystal material with an applied electric field. For this purpose, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix pattern, and a driving circuit for driving the liquid crystal display panel. Specifically, the liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer for maintaining a cell gap between the array substrates, and a liquid crystal injected within the cell gap. The color filter array substrate includes a color filter including liquid crystal cells, a black matrix reflecting external light and separating the color filters, a common electrode supplying a reference voltage to the liquid crystal cells, and an alignment film applied on the liquid crystal cells.
The thin film transistor array substrate includes gate lines and data lines. Thin film transistors are formed as switching devices at every crossing of the gate lines and the data lines. Pixel electrodes are respectively connected to the formed thin film transistors. An alignment film is applied on the liquid crystal cells. The gate lines and the data lines receive signals from the driving circuits through each of a plurality of pad parts. Each thin film transistor supplies a pixel voltage signal to the pixel electrode in response to a scan signal provided through a gate line. The pixel voltage signal is provided through a data line.
The liquid crystal display panel is fabricated by combining the thin film transistor array substrate and the color filter array substrate, which are separately manufactured. The liquid crystal material is injected between the substrates. The substrates are then sealed with the liquid crystal material between them. When fabricating such a liquid crystal display device, since the thin film transistor array substrate involves a semiconductor process and requires a plurality of mask processes, the manufacturing process for the thin film transistor array substrate is complicated and causes high manufacturing cost for the liquid crystal display panel.
In order to reduce manufacturing cost, a reduction in the number of mask processes is sought. Because, each mask process includes many processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection processes and the like. Recently, a four mask process has been introduced. The four mask process is obtained from an existing five mask process, which is commonly used.
FIG. 1 is a plan view illustrating a portion of a thin film transistor array substrate in accordance with related art. FIG. 2 is a sectional view of the related art thin film transistor array substrate taken along the line I–I′ in FIG. 1. Referring to FIGS. 1 and 2, the thin film transistor array substrate includes gate lines 2 and data lines 4 crossing each other. A gate insulating film 44 is disposed on a lower substrate 42 between the gate lines 2 and the data lines 4. A thin film transistor 6 is formed at each crossing of the gate lines and the data lines. A pixel electrode 18 is formed in the cell region defined by the crossings of the gate lines and data lines. The thin film transistor array substrate further includes a storage capacitor 20, a gate pad part 26 and a data pad part 34. The storage capacitor 20 is formed at an overlapped part of the pixel electrode 18 and a pre-stage gate line 2. The gate pad part 26 is connected to the gate line 2. The data pad part 34 is connected to the data line 4.
The thin film transistor 6 includes a gate electrode 8, a source electrode 10, a drain electrode 12, and an active layer 14 of a semiconductor pattern 47. The gate electrode 8 is connected to the gate line 2. The source electrode 10 is connected to the data line 4. The drain electrode 12 is connected to a pixel electrode 18. The active layer 14 of semiconductor pattern 47 has a channel region defined between the source electrode 10 and the drain electrode 12, and overlaps the gate electrode 8.
The active layer 14 is overlapped by a lower data pad electrode 36, a storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12. An ohmic contact layer 48 is formed on the active layer 14. The ohmic contact layer 48 of the semiconductor pattern 47 contacts the lower data pad electrode 36, the storage electrode 22, the data line 4, the source electrode 10, the drain electrode 12. The thin film transistor 6, in response to the gate signal supplied to the gate line 2, charges and maintains a pixel voltage signal, which is supplied through the data line 4, in the pixel electrode 18.
The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 16 passing through a passivation film 50. The pixel voltage charged across the pixel electrode 18 causes a potential difference with respect to the common electrode formed on an upper substrate (not shown). The liquid crystal material located between the thin film transistor substrate and the upper substrate rotates under the influence of this potential difference, due to a dielectric anisotropy. The rotated crystal material transmits incident light emitted by the light source (not shown) to the upper substrate through the pixel electrode 18.
The storage capacitor 20 includes a pre-stage gate line 2, a storage electrode 22, and the pixel electrode 18. The storage electrode 22 overlaps the pre-stage gate line 2 with the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween. The pixel electrode 18 is connected through a second contact hole 24 formed at the passivation film 50 and overlaps the storage electrode 22 having the passivation film 50 therebetween. The storage capacitor 20 charges the pixel voltage to the pixel electrode 18 and maintains a stable voltage until a next pixel voltage is charged.
The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad part 26 includes a lower gate pad electrode 28 and an upper gate pad electrode 32. The lower gate pad electrode 28 extends from the gate line 2. The upper gate pad electrode 32 is connected to the lower gate pad electrode 28 via a third contact hole 30, which passes through both of the gate insulating film 44 and the passivation film 50.
The data line 4 is connected to a data driver (not shown) through the data pad part 34. The data pad part 34 includes the lower data pad electrode 36 and an upper data pad electrode 40. The lower data pad electrode 36 extends from the data line 4. The upper data pad electrode 40 is connected to the lower data pad electrode 36 via a fourth contact hole 38 passing through the passivation film 50. The thin film transistor substrate having the above-mentioned configuration is formed through the use of the four mask process.
FIGS. 3A to 3D are sectional views sequentially illustrating a method of manufacturing the related art thin film transistor array substrate shown in FIG. 2. Referring to FIG. 3A, gate patterns are formed on the lower substrate 42. A gate metal layer is formed on the lower substrate 42 by a deposition method, such as sputtering. The gate metal layer is subsequently patterned by a photolithography process using a first mask and an etching process to thereby form the gate patterns, which include the gate line 2, the gate electrode 8 and the lower gate pad electrode 28. A material for the gate metal layer includes chrome (Cr), molybdenum (Mo), aluminium (Al) or the like, which are used in a form of a single-layer structure or a double-layer structure.
Referring to FIG. 3B, the gate insulating film 44, the active layer 14, the ohmic contact layer 48 and source/drain patterns are sequentially formed on the lower substrate 42 provided with the gate pattern. The gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially formed on the lower substrate 42 having the gate patterns thereon by a deposition technique, such as plasma enhanced chemical vapor deposition (PECVD) and sputtering.
A photo-resist pattern is formed on the source/drain metal layer by a photolithography process using a second mask. In this case, the second mask is a diffractive exposure mask having a diffractive exposing part wherein the diffractive exposing part corresponds to a channel portion of the thin film transistor. The resulting photo-resist pattern of the channel portion has a lower height than a photo-resist pattern of the source/drain pattern part.
The source/drain metal layer is subsequently patterned by a wet etching process using the photo-resist pattern, thereby forming source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the amorphous silicon layer and the n+ amorphous silicon layer are simultaneously patterned by a dry etching process using the same photo-resist pattern. The resulting semiconductor pattern 47 includes the ohmic contact layer 48 and the active layer 14. The photo-resist pattern having a relatively low height in the channel portion is removed by an ashing process and thereafter the source/drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 from the drain electrode 12. Thereafter, a remainder of the photo-resist pattern left on the source/drain pattern is removed by a stripping process.
Referring to FIG. 3C, the passivation film 50 is formed on the gate insulating film 44 including the source/drain patterns. The passivation film 50 includes first to fourth contact holes 16, 24, 30 and 38. A metal for the source/drain pattern includes chrome (Cr), titanium (Ti), tantalum (Ta) or the like. The passivation film 50 is entirely formed on the gate insulating film 44 having the source/drain patterns by a deposition technique, such as PECVD.
The passivation film 50 is subsequently patterned by photolithography using a third mask and an etching process to thereby form the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 passes through the passivation film 50 and exposes the drain electrode 12. The second contact hole 24 passes through the passivation film 50 and exposes the storage electrode 22. The third contact hole 30 passes through the passivation film 50 and the gate insulating film 44 and exposes the lower gate pad electrode 28. The fourth contact hole 38 passes through the passsivation film 50 and exposes the lower data pad electrode 36.
The gate insulating film 44 is made of an inorganic insulating material, such as silicon oxide (SiOx) or silicon nitride (SiNx). The passivation film 50 is made of an inorganic insulating material, like the gate insulating film 44, or an organic insulating material having a small dielectric constant, such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).
Referring to FIG. 3D, transparent electrode patterns are formed on the passivation film 50. More specifically, a transparent electrode material is entirely deposited on the passivation film 50 by a deposition technique, such as sputtering or the like. Then, the transparent electrode material is patterned by photolithography using a fourth mask and an etching process. The resulting transparent electrode patterns includes the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping a pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. In this connection, the transparent electrode material is made of an indium-tin-oxide (ITO), a tin-oxide (TO) or an indium-zinc-oxide (IZO).
As described above, the related art thin film transistor array substrate and the manufacturing method thereof adopts a four mask process. The four mask process simplifies the manufacturing processes compared with the five mask process and reduces manufacturing cost accordingly. However, since the four mask process is still complex and provides only limited reduction in manufacturing cost, a simpler manufacturing process with further reduction in manufacturing cost is needed.